Passive analog holding circuit



March 2, 1965 Filed D80. 31, 1959 2 Sheets-Sheet 1 FIG.2 22 26 N )1 17V J1 S? I l/ R2 R3 r FIG. 3

INVENTORS Raymond E. Banner,

Wilhelm 6.6pruf/7 7 BY 6 William R Margopou/as JWA M rw m ORNEYS United States Patent York Filed Dec. 31, 1959, Ser. No. 863,308 7 Claims. (Cl. 307-409) This invention relates generally to an analog voltage holding circuit and more specifically to a passive circuit connected to transfer electrical energy between two storage devices so that the output voltage of the circuit remains proportional to an analog input voltage long after the input voltage is removed from the circuit.

Analog voltage holding circuits are broadly well known in the prior art. However, in the past an analog voltage has been held by storing electrical energy in a device, such as a capacitor, and the development of the prior art has been directed toward circuits for keeping the energy stored in this device. The inherent problem of these prior art circuits is that a load must be connected to the storage device in order to utilize the electrical energy stored therein, and as the energy is dissipated through the load, the analog voltage across the storage device decreases and remains substantially equal to the original input analog voltage for only a relatively short time. Therefore, it is the principal object of this invention to provide an analog holding circuit in which the stored energy is purposely discharged from a storage device in order to lengthen the time during which the output voltage of the circuit remains substantially equal or proportional to an input voltage.

Another object of this invention is to provide a circuit for charging and discharging a capacitor so that the circuit output voltage during both charging and discharging is substantially proportional to the circuit input voltage.

A further object is to provide an analog holding circuit having a first capacitor which is charged by an analog input voltage connected thereto and an output circuit including a second capacitor which is charged by the discharge of the first capacitor when the input voltage is disconnected from the circuit.

Still another object of this invention is to provide an analog holding circuit in which a capacitor charged by an input analog voltage is discharged through an output circuit having a second capacitor and a resistor connected in series so that the surrr of the voltages developed in the output circuit is proportional to the input analog voltage. 3

Other objects of the invention will be pointed out in the following description and claims and illustrated in the accompanying drawings which disclose, by way of example, the principle of the invention and the best mode which has been contemplated of applying that principle.

In the drawings:

" FIG. 1 shows a typical prior art analog holding circuit;

FIG. 2 shows a practical analog holding circuit embodying this invention;

across input terminals 10 and 12. This voltage is applied through switch S across capacitor C to charge the capacitor to a voltage equal to E E also is applied to the input of amplifier 14 whose output appears across terminals 16 and 18. The output voltage E of amplifier 14 is directly proportional to E as long as switch S is closed. A load 20 may be connected across terminals 16 and 18 and represents a utilization circuit to which B is applied. Amplifier 14 may represent the input amplifier of a following digital voltmeter or merely the input impedance 'of a network connected to the holding device.

Immediately after switch S is opened, B remains proportional to E However, the capacitor begins to discharge exponentially and, therefore, E begins to decrease accordingly. If the leakage impedance of the opened switch and the input impedance of amplifier 14 are very large, this change will be slow and a long holding time is possible. When solid state devices are used, however, both the backward impedance of the switch and the input impedance of the amplifier may not be larger than 1M which is too small to be negligible. If we assume a reasonable value for C of l uf., the discharging time constant for the capacitor is 0.5 second. This means the time during which B is accurate within 0.1 percent is only 500 ,us. which is too short for many applications. The circuit shown in FIGS. 2 and 3 enable this holding time to be lengthened considerably, the holding time in an example to be described below being 58 times longer than that of the basic circuit of FIG. 1.

A circuit embodying this invention is shown in FIG. 2 where an input analog voltage E is applied to input terminals 22 and 24 through normally closed switch S to capacitor C R and R act as a voltage divider and switch S is normally closed so that the output analog voltage E appearing across output terminals 26 and 28 is equal to the voltage drop across'R and therefore is directly proportional to E,. a

The closed position of switch S may represent the sampling time of the analog voltage E Capacitor C also charges to the voltage E while S is closed. C is connected in series with R but is bypassed by switch S When the sampling time is terminated, E is removed. This may be represented by the opening of switch S Switch S is opened simultaneously with switch S In an actual circuit S, and S may be transistor switches. When the two switches are open, capacitor C discharges through R R and C so that E is the voltage developed across R and C During discharging of C output voltage E may be'represented by the following equation:

where 1+Cs 2) "*0' .0. R2+Ra It can be seen that if R3 1 z-lz C1+C5 then E is proportional to E, and the holding time is theoretically infinite.

In actual circuit design, the circuit shown in FIG. 2 is not obtainable because of the backward impedance of the switches and the input impedance of the network connected to output terminals 26 and 28 of the holding circuit. In addition, We have to take into account that the holding circuit will have to work repetitively and, therefore, C has to be discharged at the end of each holding cycle by means of the transistor switch 5 connected across C The backward impedance of this switch will also have to be taken into account. Furthermore, it will not be possible to discharge C completely so that we have to take into account its residual voltage E A circuit taking into account all these practical considerations is shown in FIG. 3.

In FIG. 3, elements corresponding directly to elements in FIG. 2 carry the same reference characters. In addition, R represents the backward impedance of the open switch S R represents the backward impedance of open switch S and R represents the input impedance of an amplifier or other utilization network connected to terminals 26 and 28.

The output voltage E for the circuit shown in FIG. 3 is represented by the following equation:

where B is the residual voltage across capacitor C at 1:0 (when S is first opened) due to an incomplete discharge at the end of the previous cycle, and D, F, G, H, 6 and 6 are constants determined by the values of the resistances and capacitors of the circuit. Equations for calculatingthese constants are presented below.

The above equation may be simplified by using a series for the general term 06 as follows For a holding circuit operating with a 0.1 percent accuracy, the time constants 1/6 and 1/5 must be considerably larger than the maximum holding time of the circuit. In other Words,

If We then neglect the residual voltage E appearing across capacitor C at 1:0, it can then be shown that the output voltage E is proportional to the input Voltag E; if C has the following value:

Using this value of C it would appear that E does not change at all with time, but such a result is true only so long as the assumption 6 t remains valid. For a somewhat longer holding time, we must take the square component, 6 2 into account. Once again assuming that E 0, it can be shown that the output voltage E is represented by the following equation.

(8) E =E H (1' /2 Bt where B is a constant determinedby the values of the resistances and capacitors in the circuit and may be calculated by an equation presented below.

If we now assume some actual values for the circuit components of FIGURE 3, the holding time for 0.1 percent accuracy may be easily determined. Let us assume that the resistors of FIGURE 3 have a value of 1M and capacitor C has a value of 1 ,af. Capacitor C may then be calculated to have a value of 0.2 of. The calculated maximum holding time within 0.1 percent accuracy is, therefore,

4 may be increased even more as shown by the plot of FIG. 5. As this plot shows, the output voltage E may actually be caused to rise above the input voltage E for a portion of the time between t:0 when switch S is opened and the maximum holding time i reaching a maximum at some time t This time t may be calculated by differentiating the general Equation 4 represent ing the circuit shown in FIG. 3.

For E assumed to be zero, then The value of k is equal to the percent accuracy required divided by 100, i.e., k=10- in FIG. 5. After the desired value of k is selected, C may be varied to obtain this value. The maximum holding time may then be determined by i /2 10+ 10* iiitr+ m By making some valid assumptions, the approximate optimum value of C may be determined from the following equation:

and k are not functions of C and can be easily determined by combining the C term in Equations 12 through 17. The assumptions referred to above are that k k and k, are all of the same order of magnitude and all much less than k which in turn is of the order of magnitude of k and k l.

Once again, assuming that the resistors in FIG. 3 have a value of 1M and C has a value of 1 .f., C may be calculated to be 0.180 ,u.f. for k= The time at which the peak value occurs in the plot of FIG. 5 may be calculated to be t =11.0 ms. The maximum holding time for 0.1 percent accuracy may be calculated to be t =26.6 ms. The holding time then for a circuit operating in accordance with the plot of FIG. 5 is about twice as long as that for a circuit operating in accordance with FIG. 4.

Further improved holding can be obtained by feeding output E of the holding circuit in FIG. 3 to an amplifier whose output is E Normally, this amplifier will provide a gain of '1/H (H is an attenuation constant and equals 3) for the chosen values of FIG. 3 to compensate for the loss in the holding circuit. In the plot of FIG. 4, the maximum value at 1 was made equal to l+10- If, however, the gain of the amplifier is'reduced to and C is calculated for k=2 10 a greater holding time may be obtained by using the output E of amplifier 30. For this condition, C =0.172 i, the time of the peak t =l4.5 ms., and the maximum holding time t =29 ms. Therefore, the holding time has been increased by about 3 ms. By increasing the holding time to this degree, the effect of the 6 t in Equation 5 may not be negligible and may effect the accuracy of the above value for t and, therefore, the 29 ms. value should be taken as an indication of order of magnitude.

As a practical matter, in practicing this invention C may be calculated to obtain an approximate optimum value, and then a trimmer capacitor may be connected in parallel with C and varied to obtain the best value of capacitance.

If we did not use the holding circuit of FIG. 3, but instead a simple 1 f. capacitor, this capacitor would discharge through the two parallel lM resistors R and R The time constant for the discharging capacitor would be 0.5 second and the holding time within 0.1 percent accuracy would be only 0.5 ms. Thus, the holding circuit of FIG. 3 increases the holding time a maximum of 5 8 times for the chosen values.

We have used numerical values in describing a specific embodiment of this invention, however, it should be stressed that very similar results can be obtained by using other values for the resistors and capacitors in accordance with the equations presented above.

As a practical matter, an output amplifier would normally be connected to the output of the holding circuit shown in FIG. 3. The resistors R R R and R act as a voltage divider and thus E will be only a fraction of E. For example, with the previously discussed numerical values for the resistors, E =%E Therefore, the output amplifier is necessary to raise E back to the original input voltage level. An output amplifier will, however, be necessary in most applications in any event to match the input impedance of the following network connected to the holding circuit. It is then only necessary to increase the gain of the amplifier to 3 instead of 1 as when only an impedance match is necessary.

Since the holding circuit will have to work normally in repetitive cycles, it may be diflicult to discharge C completely. However, R R and R serve as a voltage divider and, therefore, only a fraction of B will appear at the output terminals of the holding circuit. If, for example, we have an output voltage range of 10 mv. to 10 v. and a 0.1 percent accuracy is required, it can be calculated by Equation 4 that E should be smaller than 30 mv. For other values of R R and R the tolerable residual voltage across C may be greater or smaller.

It is completely possible to use 10 percent tolerance circuit components since the final compensation can be achieved by selecting the correct value for C However, the actual value of resistors and capacitors should not change appreciably with time. An analysis of the change which can be tolerated may be made by the use of partial derivatives.

In order to obtain an order of magnitude for the effect of component variation with time, the case of FIG. 4 has been analyzed. In this case Q=0, t =12.5 ms., and for the assumed circuit components, the percentage change in the output voltage E becomes (Percent E )=.00975 (percent R ).6534(percent R .0238(percent R )+.0077(percent R .0O195 (percent R +.0226(percent C ).0164(percent C It can be seen that the most critical parameter is R This is due to its effect on H, the attenuation of the holding circuit.

If it is assumed that all component variations arerandom and statistically independent and that the percentage value of the variable represents the standard deviation about the mean, the standard deviation of E about its mean can be obtained for small deviations by the sum of the square rule. When the following standard deviations are assumed (26) Percent R =5 Percent R =.1 Percent R =.1 Percent R =.1 Percent R =5 Percent C =1 Percent C :1

The result is (27) (Percent E =.0866

Therefore, if the change accuracies of Equations 26 prevail, E will always be within its 0.1% limitation for small t and the holding time could be either increased or decreased from its mean of 12.5 ms.

If the accuracies of R and R were changed to 1% and .0l%, respectively, the accuracy of E would improve to (28) (Percent E =.0344

The switches S and S may be in the form of a transistor, electronic tube, cryogenic device or magnetic device. An actual test circuit incorporating transistor switches is shown in FIG. 6. TR-l and TR-Z are NPN transistors corresponding respectively to switches S and S in FIG. 2. A square wave generator 32 supplies switching pulses to the bases of TR-l and TR-2 in order to turn these transistors on and off. TR-1 is used to discharge C whose charging and discharging times are both equal to 30 ms. TR-2 discharges C after each holding cycle down to a voltage of 12 mv. within a time of about ,uS,

While there have been shown and described and pointed out the fundamental novel features of the invention as applied to the preferred embodiment, it will be understood that various omissions and substitutions and changes in the form and details of the device illustrated and in its operation may be made by those skilled in the art Without departing from the spirit of the invention. It is the intention, therefore, to be limited only as indicated by the scope of the following claims.

What is claimed is:

'1. A passive electrical analog holding circuit comprising a source of voltage, a first electrical energy storage means connected across said source, a pair of output terminals, an output circuit connected to said first storage means and across said output terminals, said output circuit including a second electrical energy storage means and a resistive impedance connected in series, means for disconnecting said source from said first storage means and for transferring the electrical energy stored in said first storage means through said resistive impedance to said second storage means so that the voltage developed across said output terminals is substantially proportional to the voltage of said source both before and after said source is disconnected from said first storage means.

2. A passive electrical analog holding circuit comprising a first capacitor, a pair of output terminals, an output circuit connected across said first capacitor and said output terminals, said output circuit including a second capacitor and a resistor connected in series, means for connecting an analog voltage to said first capacitor to charge said first capacitor and cause current to flow through said resistor, and switching means operative simultaneously to disconnect said analog voltage and connect said first capacitor to said second capacitor so that said first capacitor discharges through said resistor and into said second capacitor, whereby the voltage developed across said output terminals both before and after the operation of said switching means is proportional to said analog voltage.

3. An electrical analog holding circuit comprising a first capacitor, a first resistor connected to said first capacitor, an output circuit connected across said first resistor and said first capacitor, said output circuit including a second resistor and a second capacitor connected in series, a pair of output terminals connected across said output circuit, normally closed first switching means for connecting an analog voltage across said first capacitor, and normally closed second switching means for short circuiting said second capacitor so that when said first and second switching means open simultaneously, said first capacitor discharges through said second resistor and into said second capacitor whereby the voltage developed across said output circuit is substantially proportional to said analog voltage both before and after said first and second switching means are open.

4. An electrical analog holding circuit comprising a source of analog voltage, a'first capacitor, normally closed first switching means connecting said source to one side of said capacitor, a first resistor having one end connected to said source and to said one side of said capacitor, an output circuit connected between the other end of said first resistor and the other side of said first capacitor, said output circuit including a second resistor and a second capacitor connected in series, a pair of output terminals connected across said output circuit, second normally closed switching means shunting said second capacitor, and means for simultaneously opening said first and second switching means to cause said first capacitor to discharge through said first and second resistors and into said second capacitor so that the voltage developed across said output terminals remains substantially proportional to said analog voltage even though said source is disconnected from said first capacitor.

5. An electrical analog holding circuit as defined in claim 4 wherein said second capacitor has a smaller value of capacitance than said first capacitor.

6. An electrical analog holding circuit as defined in claim 4 wherein said first and second switching means are transistors.

7. A passive electrical analog voltage circuit as defined in claim 1 wherein each of said first and second storage means includes a capacitor.

References Cited in the file of this patent UNITED STATES PATENTS 2,470,895 Marlowe et al May 24, 1949 2,572,080 Wallace Oct. 23, 1951 2,889,470 Gray June 2, 1959 2,892,106 Giori June 23, 1959 2,932,017 Prince Apr. 5, 1960 2,999,208 Ruehleman Sept. 5, 1961 UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No. 3,171,986 March 2, 1965 Raymond E. Bonner et a1.

It is hereby certified that'error appears in the above numbered patent requiring correction and that the said Letters Patent should read as corrected below.

Column 2, equation (1), for that port'i'o'n'o'f'the equation reading )q il' column 3, equation (5) for that portion of the equation reading i read same column 3, equation (6) for that portion of the equation reading I read I 1 column 4, equation (20), for that portion of the equation reading 2 (k-F10' read 2(k1103) same column 4, equation (21), for that portion of the equation readlng read [1+- column 5, equation (L22) the equation's'houl'd appear as shown below instead of as in -the patent:

same columnS, line 44, for "effect" read affect column pp'ear'as shown below 6, equation quation s'hould a instead of as in the patent (Percent E )=.0866

Signed and sealed this 7th day of December 1965.

(SEAL) Attest:

ERNEST W. SWIDER EDWARD J. BRENNER Attesting Officer Commissioner of Patents 

1. A PASSIVE ELECTRICAL ANALOG HOLDING CIRCUIT COMPRISING A SOURCE OF VOLTAGE, A FIRST ELECTRICAL ENERGY STORAGE MEANS CONNECTED ACROSS SAID SOURCE, A PAIR OF OUTPUT TERMINALS, AN OUTPUT CIRCUIT CONNECTED TO SAID FIRST STORAGE MEANS AND ACROSS SAID OUTPUT TERMINALS, SAID OUTPUT CIRCUIT INCLUDING A SECOND ELECTRICAL ENERGY STORAGE MEANS AND A RESISTIVE IMPEDANCE CONNECTED IN SERIES, MEANS FOR DISCONNECTING SAID SOURCE FROM SAID FIRST STORAGE MEANS AND FOR TRANSFERRING THE ELECTRICAL ENERGY STORED IN SAID FIRST STORAGE MEANS THROUGH SAID RESISTIVE IMPEDANCE TO SAID SECOND STORAGE MEANS, SO THAT THE VOLTAGE DEVELOPED ACROSS SAID OUTPUT TERMINALS IS SUBSTANTIALLY PROPORTIONAL TO THE VOLTAGE OF SAID SOURCE BOTH BEFORE AND AFTER SAID SOURCE IS DISCONNECTED FROM SAID FIRST STORAGE MEANS. 